Dr. Jeyavijayan “JV” Rajendran is partnering with Intel Corporation for the DARPA-Structured Array Hardware for Automatically Realized Applications (SAHARA) project. The three-year partnership enables the design of custom computer chips that incorporate advanced security countermeasure technologies for widespread applications, including government security.
The SAHARA project is facilitating the automated conversion of field-programmable gate arrays (FPGAs), which provide basic functionality that can be modified post-production into secure application-specific integrated circuits (ASICs), providing fixed functionality. This integration will strengthen the security of the processors and improve overall performance.
“What Intel is doing with this ASIC technology is they are taking the best of both worlds, where you can have the configurability of FPGA style but close to ASIC-like performance,” Rajendran said.
Rajendran explained that this project will bolster the semiconductor industry and have widespread impact in industries, such as the smart grid and other critical infrastructure elements.
“The goal of the SAHARA program is to utilize structured ASICs to meet the performance and security needs of the electronic components used in diverse Department of Defense applications,” said Kostas Amberiadis, ASIC design engineer at Intel Corporation.
“SAHARA aims to enable a 60% reduction in design time, a 10-times reduction in engineering costs and a 50% reduction in power consumption by automating the FPGA-to-structured-ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office, when announcing the project.
Rajendran’s students and postdoctoral researchers are also working closely with Intel on this project and receiving invaluable experience at this stage of their academic and professional careers to bridge the gap between academia and industry.